1. Field of the Invention
This invention relates to integrated circuit structures formed on a semiconductor wafer. More particularly, this invention relates to an integrated circuit structure having a floating electrode with a discontinuous metal silicide surface formed thereon, and a process for forming same.
2. Description of the Related Art
In the formation of integrated circuit structures on semiconductor wafers, it is sometimes desirable to provide, on a conductive element such as an electrode, a roughened surface with high electric field regions. Such a roughened surface, for example, is useful on the surface of a floating gate facing the control gate in an erasable programmed read only memory (EPROM) device. Such a roughened surface, or asperities, formed on the floating gate of an EPROM device cause a controlled breakdown of the oxide at a lower voltage between the floating gate and the control gate, due to Fowler-Norheim tunneling, rather than a destructive breakdown through the oxide during discharge of the floating gate electrode. However, such formation of a roughened surface of controlled texture and high dielectric field points, for example, on a metal or silicon surface, is not always easily accomplished reliably and reproducibly.
Faraone U.S. Pat. No. 4,735,919; Fujii et al. U.S. Pat. No. 5,017,505; and Hazani U.S. Pat. No. 5,087,583 all teach the formation of a floating gate electrode with a roughened surface thereon. In the Faraone and Hazani patents, a thermal oxide layer is grown on the surface of a polysilicon electrode, resulting in a roughened interface between the thermal oxide layer and the polysilicon. The thermal oxide layer is then removed, leaving a roughened surface on the remaining polysilicon electrode. In the Fujii et al. patent, the roughened surface is formed on the polysilicon by controlling the deposition temperature and a subsequent oxide layer is placed over the roughened polysilicon surface to replicate the roughness in the oxide layer, thereby permitting a subsequent polysilicon layer to be formed over the surfaced-roughened oxide layer to provide a polysilicon layer with its undersurface roughened.
It is also known to form a metal silicide layer over a polysilicon layer to form a roughened surface either in the metal silicide or in the underlying polysilicon layer, when it is desirable to form a capacitor of extended surface area. Lu U.S. Pat. No. 5,110,752 teaches the formation of a roughened polysilicon electrode for use in forming a capacitor of extended surface area. A silicide-forming metal is deposited over a polysilicon layer and the composite layer is then heated to form a metal silicide. The metal silicide is then removed, leaving a toughened surface on the remaining polysilicon layer, which forms one electrode of the capacitor.
Doan U.S. Pat. No. 5,223,081 discloses a process for roughening and increasing the surface area of a silicon or polysilicon substrate of a semiconductor by forming a thin metal layer such as titanium over a substrate which may be silicon or polysilicon; heating the metal layer and substrate sufficiently to cause a chemical reaction between the substrate and the metal layer to form a silicide layer and a thin layer of metal oxide-nitride on the silicide layer; then removing the metal oxide-nitride layer, for example, with a solution of ammonium hydroxide and hydrogen peroxide; and then removing the silicide with an etch such as, for example, an HF acid dip; leaving a rough and irregular surface on the remaining silicon or polysilicon. The resultant roughened surface is said to be useful not only to increase surface area and therefore capacitance of a DRAM storage cell; but also to provide better adhesion for conductors or insulators; to reduce reflective notching in photolithography; and to improve the efficiency of solar cells.
Chhabra et al. U.S. Pat. No. 5,182,232 discloses the texturizing of a surface of a conductive structure to increase the storage capacitance of a capacitor made using the texturized conductive structure as an electrode of the capacitor. A layer of polysilicon is first deposited followed by deposition of a metal silicide layer, preferably a silicon-rich metal silicide. The structure is then annealed to alter the grain size of the metal silicide and create silicon-rich grain boundaries. A wet etch is then conducted to remove the silicon in the grain boundaries thereby texturizing the surface of the remaining metal silicide. The process is said to be directed to a conventional stacked capacitor DRAM fabrication process, or to a variety of semiconductor devices (such as VRAMs or EPROMs) and their subsequent fabrication processes, where polysilicon is used as a semiconductor and a metal silicide may be added to enhance conductivity, such as the capacitor cell plates of a storage capacitor and where it is desirable to have the conductor surface take on a texturized surface.